How to make any AMD Zen CPU always generate 4 from RDRAND
(theregister.com)
Googlers have not only figured out how to break AMD's security – allowing them to load unofficial microcode into its processors to modify the silicon's behavior as they wish – but also demonstrated this by producing a microcode patch that makes the chips always output 4 when asked for a random number.
Googlers have not only figured out how to break AMD's security – allowing them to load unofficial microcode into its processors to modify the silicon's behavior as they wish – but also demonstrated this by producing a microcode patch that makes the chips always output 4 when asked for a random number.
New speculative attacks on Apple CPUs
(predictors.fail)
We present SLAP, a new speculative execution attack that arises from optimizing data dependencies, as opposed to control flow dependencies. More specifically, we show that Apple CPUs starting with the M2/A15 are equipped with a Load Address Predictor (LAP), which improves performance by guessing the next memory address the CPU will retrieve data from based on prior memory access patterns.
We present SLAP, a new speculative execution attack that arises from optimizing data dependencies, as opposed to control flow dependencies. More specifically, we show that Apple CPUs starting with the M2/A15 are equipped with a Load Address Predictor (LAP), which improves performance by guessing the next memory address the CPU will retrieve data from based on prior memory access patterns.
Disabling Zen 5's Op Cache and Exploring Its Clustered Decoder
(chipsandcheese.com)
Zen 5 has an interesting frontend setup with a pair of fetch and decode clusters. Each cluster serves one of the core’s two SMT threads. That creates parallels to AMD’s Steamroller architecture from the pre-Zen days. Zen 5 and Steamroller can both decode up to eight instructions per cycle with two threads active, or up to four per cycle for a single thread.
Zen 5 has an interesting frontend setup with a pair of fetch and decode clusters. Each cluster serves one of the core’s two SMT threads. That creates parallels to AMD’s Steamroller architecture from the pre-Zen days. Zen 5 and Steamroller can both decode up to eight instructions per cycle with two threads active, or up to four per cycle for a single thread.
Skymont: Intel's E-Cores reach for the Sky
(chipsandcheese.com)
The 2020s were a fun time for Intel’s Atom line, which went from an afterthought to playing a major role across Intel’s high performance client offerings.
The 2020s were a fun time for Intel’s Atom line, which went from an afterthought to playing a major role across Intel’s high performance client offerings.
If GPUs Are So Good, Why Do We Still Use CPUs at All?
(codingstuff.substack.com)
There’s this old video from 2009 that’s been going viral on Twitter recently. Its supposed to give viewers an intuition of the difference between CPUs and GPUs.
There’s this old video from 2009 that’s been going viral on Twitter recently. Its supposed to give viewers an intuition of the difference between CPUs and GPUs.
Fujitsu's Monaka CPU: ARMv9, SVE2, and 3D Stacking
(chipsandcheese.com)
Hello you fine Internet folks, today we are going back to SC24 with a short about Fujitsu’s upcoming Monaka CPU.
Hello you fine Internet folks, today we are going back to SC24 with a short about Fujitsu’s upcoming Monaka CPU.
Turning Off Zen 4's Op Cache for Curiosity and Giggles
(chipsandcheese.com)
CPUs start executing instructions by fetching those instruction bytes from memory and decoding them into internal operations (micro-ops). Getting data from memory and operating on it consumes power and incurs latency. Micro-op caching is a popular technique to improve on both fronts, and involves caching micro-ops that correspond to frequently executed instructions.
CPUs start executing instructions by fetching those instruction bytes from memory and decoding them into internal operations (micro-ops). Getting data from memory and operating on it consumes power and incurs latency. Micro-op caching is a popular technique to improve on both fronts, and involves caching micro-ops that correspond to frequently executed instructions.
An EPYC Exclusive for Azure: AMD's MI300C – By George Cozma
(chipsandcheese.com)
At SC24 we stopped by the Azure Booth to check out their new HBv5 VMs powered by the AMD EPYC 9v64H CPU.
At SC24 we stopped by the Azure Booth to check out their new HBv5 VMs powered by the AMD EPYC 9v64H CPU.
AMD Disables Zen 4's Loop Buffer
(chipsandcheese.com)
A loop buffer sits at a CPU's frontend, where it holds a small number of previously fetched instructions. Small loops can be contained within the loop buffer, after which they can be executed with some frontend stages shut off. That saves power, and can improve performance by bypassing any limitations present in prior frontend stages. It's an old but popular technique that has seen use by Intel, Arm, and AMD cores.
A loop buffer sits at a CPU's frontend, where it holds a small number of previously fetched instructions. Small loops can be contained within the loop buffer, after which they can be executed with some frontend stages shut off. That saves power, and can improve performance by bypassing any limitations present in prior frontend stages. It's an old but popular technique that has seen use by Intel, Arm, and AMD cores.
Antenna Diodes in the Pentium Processor
(righto.com)
I was studying the silicon die of the Pentium processor and noticed some puzzling structures where signal lines were connected to the silicon substrate for no apparent reason.
I was studying the silicon die of the Pentium processor and noticed some puzzling structures where signal lines were connected to the silicon substrate for no apparent reason.
IBM Power11 CPUs Launching 2025 – Linux 6.13 Preps KVM Nested Guests for Power11
(phoronix.com)
IBM isn't formally releasing Power11 processors until next year, but their software engineers continue being quite busy preparing the Linux kernel and other open-source software for Power11. The newest on the kernel side is enabling support for KVM nested guests on IBM Power11 platforms.
IBM isn't formally releasing Power11 processors until next year, but their software engineers continue being quite busy preparing the Linux kernel and other open-source software for Power11. The newest on the kernel side is enabling support for KVM nested guests on IBM Power11 platforms.
AMD Ryzen 7 9800X3D Linux Performance: Zen 5 With 3D V-Cache
(phoronix.com)
Ahead of tomorrow's availability of the AMD Ryzen 7 9800X3D processor as the first Zen 5 CPU released with 3D V-Cache, today the review embargo lifts. Here is a look at how this 8-core / 16-thread Zen 5 CPU with 64MB of 3D V-Cache is performing under Ubuntu Linux compared to a variety of other Intel Core and AMD Ryzen desktop processors.
Ahead of tomorrow's availability of the AMD Ryzen 7 9800X3D processor as the first Zen 5 CPU released with 3D V-Cache, today the review embargo lifts. Here is a look at how this 8-core / 16-thread Zen 5 CPU with 64MB of 3D V-Cache is performing under Ubuntu Linux compared to a variety of other Intel Core and AMD Ryzen desktop processors.
Fujitsu, AMD Plan to Pair Monaka CPUs with Instinct GPUs
(theregister.com)
Fujitsu and AMD announced plans on Friday to develop a new, more energy-efficient AI and HPC compute platform that will pair the Japanese tech vendor's next-gen CPUs with the House of Zen's Instinct accelerators.
Fujitsu and AMD announced plans on Friday to develop a new, more energy-efficient AI and HPC compute platform that will pair the Japanese tech vendor's next-gen CPUs with the House of Zen's Instinct accelerators.
MikroTik and Ampere co-developing a product line with server-class CPUs
(mikrotik.com)
Riga, Latvia & Santa Clara, CA, USA – MikroTik, a leading European IT manufacturer, and Ampere®️, an innovative US-based leader in Cloud Native Processors, are proud to announce a collaboration to develop a new line of products featuring state-of-the-art server-class CPUs that will push the boundaries of cost-effective, efficient, and powerful networking.
Riga, Latvia & Santa Clara, CA, USA – MikroTik, a leading European IT manufacturer, and Ampere®️, an innovative US-based leader in Cloud Native Processors, are proud to announce a collaboration to develop a new line of products featuring state-of-the-art server-class CPUs that will push the boundaries of cost-effective, efficient, and powerful networking.
Cyrix 6x86
(wikipedia.org)
The Cyrix 6x86 is a line of sixth-generation, 32-bit x86 microprocessors designed and released by Cyrix in 1995.
The Cyrix 6x86 is a line of sixth-generation, 32-bit x86 microprocessors designed and released by Cyrix in 1995.
A closer look at Intel and AMD's different approaches to gluing together CPUs
(theregister.com)
Shortly after the launch of AMD's first-gen Epyc processors codenamed Naples in 2017, Intel quipped that its competitor had been reduced to gluing a bunch of desktop dies together in order to stay relevant.
Shortly after the launch of AMD's first-gen Epyc processors codenamed Naples in 2017, Intel quipped that its competitor had been reduced to gluing a bunch of desktop dies together in order to stay relevant.
RISC-V is currently slow compared to modern CPUs
(benhouston3d.com)
After watching the rise of ARM displace Intel from most of my personal and server computing, I've been following the RISC-V architecture with intense interest. It's an exciting open-source ISA that has the potential to reshape the CPU landscape, but there's an important caveat: RISC-V is currently quite slow compared to modern CPUs in 2024. It is even slow compared to Raspberry PI boards.
After watching the rise of ARM displace Intel from most of my personal and server computing, I've been following the RISC-V architecture with intense interest. It's an exciting open-source ISA that has the potential to reshape the CPU landscape, but there's an important caveat: RISC-V is currently quite slow compared to modern CPUs in 2024. It is even slow compared to Raspberry PI boards.