Branch Privilege Injection: Exploiting branch predictor race conditions
(ethz.ch)
Branch Privilege Injection (CVE-2024-45332) brings back the full might of branch target injection attacks (Spectre-BTI) on Intel. Intel’s hardware mitigations against these types of attacks have held their ground for almost 6 years. In our work, we demonstrate how these mitigations can be broken due to a race condition in Intel CPUs.
Branch Privilege Injection (CVE-2024-45332) brings back the full might of branch target injection attacks (Spectre-BTI) on Intel. Intel’s hardware mitigations against these types of attacks have held their ground for almost 6 years. In our work, we demonstrate how these mitigations can be broken due to a race condition in Intel CPUs.
Reverse engineering the 386 processor's prefetch queue circuitry
(righto.com)
In 1985, Intel introduced the groundbreaking 386 processor, the first 32-bit processor in the x86 architecture.
In 1985, Intel introduced the groundbreaking 386 processor, the first 32-bit processor in the x86 architecture.
Why Intel Deprecated SGX?
(hardenedvault.net)
The rumors about Intel SGX deprecated in new processors has been confirmed, 12th generation processors (Workstation/Desktop/Laptop/embedded platforms) will deprecate SGX and the SGX will continue to support only in high-end Xeon CPU for server:
The rumors about Intel SGX deprecated in new processors has been confirmed, 12th generation processors (Workstation/Desktop/Laptop/embedded platforms) will deprecate SGX and the SGX will continue to support only in high-end Xeon CPU for server:
The complicated circuitry for the 386 processor's registers
(righto.com)
The groundbreaking Intel 386 processor (1985) was the first 32-bit processor in the x86 architecture.
The groundbreaking Intel 386 processor (1985) was the first 32-bit processor in the x86 architecture.
Zhaoxin's KX-7000
(chipsandcheese.com)
Zhaoxin is a Chinese x86 CPU designer. The KaiXian KX-7000 is Zhaoxin’s latest CPU, and features a new architecture dubbed “世纪大道”. 世纪大道 is a road in Shanghai called “Century Avenue”, following Zhaoxin’s practice of naming architectures after Shanghai landmarks. Zhaoxin is notable because it’s a joint venture between VIA Technologies and the Shanghai municipal government. It inherits VIA’s x86-64 license, and also enjoys powerful government backing.
Zhaoxin is a Chinese x86 CPU designer. The KaiXian KX-7000 is Zhaoxin’s latest CPU, and features a new architecture dubbed “世纪大道”. 世纪大道 is a road in Shanghai called “Century Avenue”, following Zhaoxin’s practice of naming architectures after Shanghai landmarks. Zhaoxin is notable because it’s a joint venture between VIA Technologies and the Shanghai municipal government. It inherits VIA’s x86-64 license, and also enjoys powerful government backing.
Show HN: I486SX_soft_FPU – Software FPU Emulator for NetBSD 10 on 486SX
(github.com/mezantrop)
This retro-computing project restores support for x87 floating-point unit (FPU) emulation in the NetBSD kernel, targeting legacy 486SX-class processors without hardware FPUs.
This retro-computing project restores support for x87 floating-point unit (FPU) emulation in the NetBSD kernel, targeting legacy 486SX-class processors without hardware FPUs.
A 32-bit processor made with an atomically thin semiconductor
(arstechnica.com)
On Wednesday, a team of researchers from China used a paper published in Nature to describe a 32-bit RISC-V processor built using molybdenum disulfide instead of silicon as the semiconductor.
On Wednesday, a team of researchers from China used a paper published in Nature to describe a 32-bit RISC-V processor built using molybdenum disulfide instead of silicon as the semiconductor.
IBM Announces the Z17 Mainframe Powered by Telum II Processors
(phoronix.com)
Following IBM engineers doing a lot of open-source compiler work around a new "arch15" that we suspected to be IBM z17 with Telum II processors, this morning IBM officially announced their next-generation mainframe hardware.
Following IBM engineers doing a lot of open-source compiler work around a new "arch15" that we suspected to be IBM z17 with Telum II processors, this morning IBM officially announced their next-generation mainframe hardware.
Loongson teases trio of new processors for lappies, factories, maybe servers too
(theregister.com)
Chinese chip designer Loongson, whose products have been promoted by Beijing, has teased two new designs that will make it more of a contender for mobile and industrial applications. It may also have a new server up its sleeve.
Chinese chip designer Loongson, whose products have been promoted by Beijing, has teased two new designs that will make it more of a contender for mobile and industrial applications. It may also have a new server up its sleeve.
Notes on the Pentium's microcode circuitry
(righto.com)
Most people think of machine instructions as the fundamental steps that a computer performs. However, many processors have another layer of software underneath: microcode. With microcode, instead of building the processor's control circuitry from complex logic gates, the control logic is implemented with code known as microcode, stored in the microcode ROM. To execute a machine instruction, the computer internally executes several simpler micro-instructions, specified by the microcode.
Most people think of machine instructions as the fundamental steps that a computer performs. However, many processors have another layer of software underneath: microcode. With microcode, instead of building the processor's control circuitry from complex logic gates, the control logic is implemented with code known as microcode, stored in the microcode ROM. To execute a machine instruction, the computer internally executes several simpler micro-instructions, specified by the microcode.
Intel AVX10 Drops Optional 512-Bit: No AVX10 256-Bit Only E-Cores in the Future
(phoronix.com)
Intel updated their AVX10 whitepaper and associated open-source compiler patches around this next Advanced Vector Extensions standard... While AVX10 had intended to allow either 256-bit or 512-bit modes depending upon processor capabilities, Intel has dropped the 256-bit-only approach and going for 512-bit everywhere.
Intel updated their AVX10 whitepaper and associated open-source compiler patches around this next Advanced Vector Extensions standard... While AVX10 had intended to allow either 256-bit or 512-bit modes depending upon processor capabilities, Intel has dropped the 256-bit-only approach and going for 512-bit everywhere.
AMD's Strix Halo under the hood
(chipsandcheese.com)
At CES 2025 I got the chance to sit down with Mahesh Subramony, AMD Senior Fellow, to talk about AMD's upcoming Strix Halo SoC which is a brand new type of product for AMD and is the big iGPU SoC that many of us have been waiting for from AMD for a long while.
At CES 2025 I got the chance to sit down with Mahesh Subramony, AMD Senior Fellow, to talk about AMD's upcoming Strix Halo SoC which is a brand new type of product for AMD and is the big iGPU SoC that many of us have been waiting for from AMD for a long while.
RISC-V Processor Design – Lec 6 – EXU and Co-Simulation
(ycombinator.com)
In this lecture, we stitch together a custom Instruction Set Simulator I created with the RISC-V CPU (now with the execution stage) and see the first instructions flowing in the pipeline.
In this lecture, we stitch together a custom Instruction Set Simulator I created with the RISC-V CPU (now with the execution stage) and see the first instructions flowing in the pipeline.
AMD EPYC 9845 Makes for a Persuasive Upgrade with Performance and Efficiency
(phoronix.com)
With the new AMD EPYC 9005 processors there are SKUs up to 500 Watt with the likes of the EPYC 9965 flagship at 192 cores for Turin Dense cores or 128 Turin classic cores with the EPYC 9755. But for those looking at upgrading from an existing EPYC 9004 series server and bound by the motherboard BIOS support and/or cooling/power capacity, 400 Watts is a sweet spot.
With the new AMD EPYC 9005 processors there are SKUs up to 500 Watt with the likes of the EPYC 9965 flagship at 192 cores for Turin Dense cores or 128 Turin classic cores with the EPYC 9755. But for those looking at upgrading from an existing EPYC 9004 series server and bound by the motherboard BIOS support and/or cooling/power capacity, 400 Watts is a sweet spot.
Apple M3 Ultra SoC: Disappointing CPU Benchmark Result Surfaces
(techpowerup.com)
Just recently, Apple somewhat stunned the industry with the introduction of its refreshed Mac Studio with the M4 Max and M3 Ultra SoCs.
Just recently, Apple somewhat stunned the industry with the introduction of its refreshed Mac Studio with the M4 Max and M3 Ultra SoCs.
Apple M3 Ultra
(apple.com)
Apple today announced M3 Ultra, the highest-performing chip it has ever created, offering the most powerful CPU and GPU in a Mac, double the Neural Engine cores, and the most unified memory ever in a personal computer.
Apple today announced M3 Ultra, the highest-performing chip it has ever created, offering the most powerful CPU and GPU in a Mac, double the Neural Engine cores, and the most unified memory ever in a personal computer.
Frameworknew Laptops AMD Ryzen AI 300 CPUs
(pcworld.com)
Today, repairable laptop maker Framework previewed the new Framework Laptop 12 — a smaller budget option — alongside a new version of its flagship Framework Laptop 13 with AMD’s recent Ryzen AI 300 series processors inside.
Today, repairable laptop maker Framework previewed the new Framework Laptop 12 — a smaller budget option — alongside a new version of its flagship Framework Laptop 13 with AMD’s recent Ryzen AI 300 series processors inside.
Intel Announces Xeon 6500P and Xeon 6700P Processors
(phoronix.com)
After launching the Intel Xeon 6900P "Granite Rapids" processors last September, today Intel is expanding the family with the launch of the Xeon 6500P and Xeon 6700P server processors.
After launching the Intel Xeon 6900P "Granite Rapids" processors last September, today Intel is expanding the family with the launch of the Xeon 6500P and Xeon 6700P server processors.
Intel Xeon 6700P and 6500P Granite Rapids-SP for the Masses Initial Benchmarks
(servethehome.com)
This Intel Xeon 6 series has been a launch we have been waiting on for around three quarters. Today, we have the launch of the Intel Xeon 6700P and Xeon 6500P series. These are the smaller Socket E2 (LGA4710-2) processors compared to the big socket Intel Xeon 6900P series. At the same time, they are not necessarily “lower-end” as they can scale to 4 sockets, eight sockets and beyond.
This Intel Xeon 6 series has been a launch we have been waiting on for around three quarters. Today, we have the launch of the Intel Xeon 6700P and Xeon 6500P series. These are the smaller Socket E2 (LGA4710-2) processors compared to the big socket Intel Xeon 6900P series. At the same time, they are not necessarily “lower-end” as they can scale to 4 sockets, eight sockets and beyond.
AVX-512 gotcha: avoid compressing words to memory with AMD Zen 4 processors
(lemire.me)
The recent AMD processors (Zen 4) provide extensive support for the powerful AVX-512 instructions.
The recent AMD processors (Zen 4) provide extensive support for the powerful AVX-512 instructions.