Hacker News with Generative AI: CPU Architecture

Zen 5's AVX-512 Frequency Behavior (chipsandcheese.com)
Zen 5 is AMD's first core to use full-width AVX-512 datapaths. Its vector execution units are 512 bits wide, and its L1 data cache can service two 512-bit loads per cycle.
CPU Architecture, Performance, AMD, Zen 5, AVX-512
213 points by matt_d 33 days ago | 66 comments
Fedora 42 Looks to Ship Optimized Executables for Different x86_64 Capabilities (phoronix.com)
Fedora Linux has already supported making use of glibc HWCAPs for allowing libraries to be built for different x86_64 micro-architecture feature levels for performance-sensitive code where it can pay off when leveraging AVX/AVX2 or other newer Intel/AMD CPU instruction set extensions. For Fedora 42 is now a proposal to extend that further to allow binary executables to also leverage glibc HWCAPs for better performance.
Linux, Operating Systems, Performance Optimization, CPU Architecture, Fedora
14 points by rbanffy 80 days ago | 2 comments
Alpine Linux 3.21: Lean, mean, and LoongArch-ready (theregister.com)
A fresh release of the minimalist and very lightweight Alpine Linux is here, with support for Chinese LoongArch64 CPUs.
Linux Distributions, Operating Systems, Hardware, CPU Architecture
6 points by LinuxBender 106 days ago | 0 comments
Exploring the Power of Parallelized CPU Architectures (meekolab.com)
In a recent trip from Japan, i came to score a rare PS3 reference tool (DECR-1000J) which was sold below market rates. As these things are apparently very rare and are not regionlocked unlike the retail models, i took the chance to buy it in order to serve as a learning platform. But unfortunately i lost the unit during a home invasion incident while i was out of the country during the weekend, alongside several valuables and my work laptop.
CPU Architecture, Hardware, Programming, Japan, Security
12 points by lnyan 126 days ago | 0 comments
Understanding SIMD: Infinite complexity of trivial problems (modular.com)
Modern CPUs have an incredible superpower: hyper-scalar operations, made available through single instruction, multiple data (SIMD) parallel processing.
CPU Architecture, Optimization, Programming
257 points by verdagon 128 days ago | 116 comments
Pushing AMD's Infinity Fabric to Its Limit (chipsandcheese.com)
I recently wrote code to test memory latency under load, seeking to reproduce data in various presentations with bandwidth on the X axis and latency on the Y axis. Ampere pretty much described how that was done during their Hot Chips 2024 presentation. To achieve the same results in a semi-automated fashion, I run a latency test thread while also running a variable number of threads that generate bandwidth load.
AMD, Memory Latency, Performance Testing, CPU Architecture
229 points by klelatti 129 days ago | 34 comments