PCIe Endpoint on Xilinx 7-Series FPGAs with PCIe_2_1 Hard Block and GTP
(github.com/regymm)
PCIe Endpoint on Xilinx 7-Series FPGAs using the PCIE_2_1 hard block and GTP transceivers. No proprietary Vivado IP cores! Compatible with openXC7!
PCIe Endpoint on Xilinx 7-Series FPGAs using the PCIE_2_1 hard block and GTP transceivers. No proprietary Vivado IP cores! Compatible with openXC7!